Electronic gang switching system



Feb. 9, 1965 w, s, MlLLER Re. 25,724

ELECTRONIC GANG SWITCHING SYSTEM Original Filed April 21, 1960 2Sheets-Sheet l INVENTOQ WENDELL .5. 2

i L I ATTOQHEY Feb. 9, 1965 w. s. MILLER ELECTRONIC GANG SWITCHINGSYSTEM 2 Sheets-Sheet 2 Original Filed April 21, 1960 INVEHTOQ $.M/ El?AT TOQHEY WENDELL United States Patent Cfiiice Re. 25,724 Reissued' Feb.9, 1965 Matter enclosed in heavy brackets appears in the 1 originalpatent but forms no part of this reissue specification; matter printedin italics indicates the additions made by reissue.

In prior electronic multipliers, it has been very difficult to attainextremely high speed operation without unduly increasing the complexityof the computing apparatus. The fastest multipliers developed to datehave been of the simultaneous operation type, in which a large number ofmultiplying circuits simultaneously perform a large number of partialmultiplications each forming a part of the overall problem. The variouspartial products are then added together to arrive at the ultimateanswer. Such simultaneous performance of all of the numerous parts of acomplex multiplication problem must of course require a very largenumber of partial product circuits, and the overall computer musttherefore be very large and expensive.

The amount of equipment required can be reduced by using, instead of thesimultaneous type of operation, a step-by-step arrangement, in which thevarious partial multiplication steps are performed sequentially, ratherthan simultaneously. Such step-by-step performance of the multiplicationproblem of course requires a considerably greater time than does thesimultaneous type of operation, and this increase in operational timebecomes a very decided disadvantage when the problem or problems to besolved are of any complexity.

A major object of the present invention is to provide an arrangement forsubstantially reducing the amount of time required in performing acomputation by the stepbystep method. This result is attained by aunique process of electronically examining the problem and automaticallyskipping over certain conventional steps which ordinarily require theexpenditure of a substantial amount of time. This skipping process isbased on the observation that usually the multiplier in a binarymultiplication problem includes a number of zeros, which zeros of courserequire no addition process to be performed at that step. The presentapparatus automatically responds to the presence of such zeros in amanner skipping completely over them, nutest delay. In many problems,very few of the possible digit circuitsare actually energized intoa'condition representing a number other than'zero, and consequently suchskipping of all of the zeros in a multiplier can reduce the number ofmultiplication steps, and the various add times required, to a smallfraction-of the time otherwise required in a conventional step-by-stepsystem. In addition to this decided advantage which is attained by mynovel computer system in a multiplication process, simi lar advantagesin reduced operational time may be attained in performing othercomputing processes.

and doing to without even the mi- Structurally, a unit embodying theinvention includes a first ordered series of input conductors or linesto which signals representing the multiplicand are applied, and a secondordered series of control conductors or lines to which signalsrepresenting the multiplier are applied. In conjunction with these inputand control conductors, there is an array of logical and circuits orelements, each of which receives a signal from one of the inputconductors and one of the control conductors. The various and 0 circuitshave associated therewith a-series of adders which are associated withditferent sets of the and circuits. To define these sets technically andprecisely, each set may be defined as including a first and circuitactuable by one of the input conductors and one of the controlconductors, and as including all and only such other and circuits as areactuable respectively by pairs of conductors including an inputconductor which is a predetermined number beyond the specified one?input conductor in the ordered series of such conductors, and a controlconductor which is the same number beyond the specified one controlconductor in the ordered series of such control conductors. As willappear, this unique arrangement provides for an automatic shifting ofthe various partial products produced on different sets of the andcircuits by the different control conductors, to give these partialproducts the proper relative weight on the ultimate adders and registersto which the final product is applied.

Certain specific features of the invention have to do with the noveltyresiding in the above discussed unique shifting or gang switchingapparatus, as such. This apparatus can be employed in various otheroverall arrangements as well as in the particular combination disclosedherein.

A feature of particular importance in the invention resides in themanner in which the control conductors are automatically scanned toattain the previously discussed zero skipping action. To achieve thisresult, there are associated with the individual control conductorsdisabling means or circuits which are automatically operable to preventthe transmission of a signal from each of predetermined sequence of suchconductors is connected to the and" circuits for transmission of asignal thereto. Also, there are provided means for ceasing thetransmission of a signal from each control conductor to the and circuitsafter the and circuits have been actuated thereby, so that the meansdisabling the next successive control conductor are automaticallyactuated to a condition permitting transmission of a signal from thatcontrol conductor to the and circuits.

The above and other features and objects of the present invention willbe better understood from the following detailed description of thetypical embodiments illustrated in the accompanying drawings in which:

first form of computer constructed in accordance with the invention;

FIG. 2 is a partial diagrammatic representation of a second form ofcomputer embodying the invention; and

FIG. 3 is a representation of the substantially rectangular hysterisloops of the magnetic cores of the FIG. 2 arrangement.

Referring first to FIG. 1, I have represented at 10a, 10b and 10c aseries of input conductors, to which electrical signals representingthree digits ofa multiplicand are supplied by three individual signalsources represented at 11a, 11b and 11c. Each of these sources 11a, 11band 11c rnay typically be actuable 'between a first condition in whichno electrical signal is applied to line 10a, 10b or 10c, to therebyrepresent the digit zero, and a second condition in which an electricalsignal is supplied to the associated line, representing the digit 1. Thethree sources are simultaneously actuable, and may be actuated in anydesired pattern, to represent any desired arrangement of the digits zeroand 1. A momentary application of a signal to any one of the lines a,16b or 10c is sufiicient to actuate the associated bi-stablemultivibrator or flipfiop circuit 12a, 12b or 12c from a first staterepresenting the digit zero to a second stable state representing thedigit 1. The bi-stable circuit 12a, 12b or 12c will then remain in thatsecond state, in spite of the termination of the signal on line 10a, 10bor 10c, and until the application of a reset signal through line 13 froma re-set signal source represented at 14. The output signals frombistable circuits 12a, 12b and 12c are applied to lines 15a, 15b and15c, which conduct the signals from the bi-stable circuits to an arrayor matrix of and circuits 16a, 16b, 16c, 16d, etc. As will be apparent,whenever one of the 1 flip-flop circuits 12a, 12b or 12c is actuated bya signal on the input line leading thereto, the flip-flop circuit actsto produce an output signal in the associated line 15a, 15b or 150.

The various digits of the multiplier are applied to a series of controlconductors 17a, 17b, 17c, 17d and 17e, which are separately energizableby a series of control signal sources 18a, 18b, etc. As in the case ofthe input conductors, each of these control conductors 17a, 17b, etc.acts when energized by a control signal to actuate an associatedbi-stable multivibrator orflip-fiop circuit 19a, 19b, 19c, 19d or 19cfrom a normal state in which no signal is provided in output line 20a,20b, 26c, 20d or 20c, to an actuated state in which an output signal. isprovided in the associated one of these output lines. The

bi-stable circuits 19a, 19b, etc. are subsequently actuable back to theoriginal state by a re-set signal applied through line 21 from a re-setsignal source represented at 22.

The output signal from each of the lines 20a, 20b, etc. is fed into anadditional and circuit 23a, 23b, 23c, 23d or 23e, which also receivesintermittent signals from a clock-pulse generator 24. The electricalsignals from the clock-pulse generator may be timed regularly orirregularly, as desired, and function intermittently to cause thetransmission of control signals to the array of and circuits 16a, 16b,16c, etc. More particularly, each of the secondary and circuits 23a,23b, 23c, etc. is adapted, in response to the application ofsimultaneous signals or pulses from clock-pulse generator 24 and theassociated line 20a, 20b, 20c, 20d, or 20e, to produce an output signalin the connected line 25a, 25b, 25c, 25d or 25c (assuming that there isno inhibiting signal applied on the later-to-be-discussed lines 29!),29c, 29d and 29e re} spectively). The output signals of these lines 25a,25b,'-

etc. are conducted to the and circuits 16a,'16b, 16c, etc. in thearrangement shown. Each of the lines 25a, 25b, 250, etc. is connected bya line 26a, 26b, 26c, 26d or 26c to the associated 'bi-stable circuit19a, 19b, etc., with delay units 27a, 27b, 27c, etc. being connectedinto these lines. Each of the lines 26a, 26b, etc. thus conducts back tothe associated flip-flop circuits 19a, 19b, etc. a signal whichautomatically re-sets that flip-flop circuit 1 0 its initial no outputstate after a suificient period of hue has expired, following theproduction of an output )3! the connected circuit 23a, 23b, etc., toprevent the aerformance of two multiplication steps on a single pulse )fthe clock-pulse generator 24.

Connected into each of the lines 20b, 20c, 20d and tile, there isprovided an and not circuit 28b, 28c, 28d )r 28c, to which disabling orinhibiting lines 29b,'29c 9d and 29e are connected. The first of thesecircuits 28b is adapted to transmit a signal to and circuit 23b 0 longas a signal is applied to its input'side 20b and |ot-to the disablingline 29b. Line 29b is electrically :onnected to the preceding or nextupper line 20a, so hat and not circuit28b will not permit a signal to beransmitted to line 25b while line 20a is energized. Simiadder 41. Thisadder 4 larly, the next lower and not circuit 28c is connected to theoutput side of an or circuit 30c, whose two inputs are connected to line20a and line 20b respectively, so that a signal is applied to inhibitingline 290 as long as either line 20a or 20b is energized, and thereforein either of these instances, it is impossible for a signal to betransmitted to and circuit 23c. Without discussing the other two and notcircuits 28d and 28c, and the other two or circuits 30d and 30e,individually, it will be apparent that each inhibiting circuit preventsthe energization of each of the lines 20b, 20c, 20d, and 20e so long asany one of the preceding (higher) lines 20a, 20b, 200, etc. is energizedby a control signal. A final or circuit 301: may connect with furtherinhibiting circuits associated with additional control conductors, ormay actuate an indicator or an automatic control represented at 31, forindicating to an operator when all of the lines 20a, Ztlb, etc. havebeen de-energized, and the multiplying operation has therefore beencompleted.

The output from and" circuit 16k is conducted by a line 32 to a halfadder 33, whose operation is timed by the pulses brought through line 34to the adder from clock-pulse generator 24. Circuit 16k is adapted toproduce an output as long as signals are supplied thereto from inputline 15c and control conductor 25a simultaneously. Each energization ofline 32, together with a pulse from clock line 34, causes adder 33 toenergize sum line 35 and thereby actuate bi-stable flip-flop circuit 36of the product register 36, 44, etc. to a condition for applying to thedigit output circuit 37 the addition product produced by adder 33.Partial product line 38, having a delay 39 connected thereinto, returnsthe product information to adder 33. The carry information istransmitted by carry line 40 to the next successive has associated withit a sum line 42, carry line 43, multi-vibrator circuit 44, outputcircuit 45, partial product digit line 46, and delay 47 corresponding tothe similar circuit elements associated with the first adder 33. Thesame is true of all of the subsequent adders 48, 49, 5t), 51 and 52,with the carry line 53 of the final adder being applied to a finalflipflop circuit 54, which controls an output circuit 55. All of theflip-flop circuits 36, 44, 54, etc. are actuable to anorrnal conditionby a re-set signal applied by a reset signal source represented at 56.The adder 33 and product register 37 normally represent the first digitof the final product of a multiplication process, while the other addersand registers 41 and 45, etc. over to 5455 represent the higher digits.For-example, output circuit 37 may represent ones, output circuit mayrepresent twos, circuit 57 may represent fours, circuit 58 may representeights, and the other output circuits may represent sixteens,thirty-twos, sixty-fours, and one-hundred twentyeights, respectively.

Full adder 41 is actuable by the output from an or circuit 59, whoseinputs come from and" circuits 16f and 161 respectively. That is,production of a signal by either of the and circuits 16f or 161(resulting from energization of the two inputs to such circuit simhltaneously) will actuate or circuit 59 to cause adder 41 to add 1 inthat place to the product represented by the register.

The third adder 48 is actuable through an or circuit 60 by energizationof any one of the three and circuits 16a, 16g or 16111. Similarly, adder49 is actuable through or circuit 61 by any one of the and circuits 15b,16h or 16n. Adder is actuable by the output from an or circuit 62, uponproduction of an output signal by any one of the and circuits 16c, hi or16p. Adder 51 is actuable through or circuit 63 by andcircuit 16d or16j, and the final adder 52 is actuable by the final and circuit 16c.

As has been mentioned previously, considering the input conductors 10a,19b and 10c as an ordered series of such conductors, and considering thecontrol conductors 17a, 17b, 17c, 17d and 17e as an ordered series ofcontrol conductors, then the sets of and circuits 16a, etc. to which thedifierent adders are responsive may be defined as follows: Each setconsists of a first and" circuit actuable by one of the input conductorsand one of the control conductors, together with all and only such otherand circuits as are actuable respectively by pairs of conductorsincluding an input conductor which is a predetermined number beyond theone input conductor in the ordered series of input conductors, and acontrol conductor which is the same number beyond the one controlconductor in the ordered series of such control conductors.

To now describe the manner of operation of the arrangement shown in FIG.1, assume that it is desired to multiply two numbers together. In theillustrated arrangement, the multiplicand may be assumed to consist ofthree digits, in binary form, while the multiplier consists of fivedigits in binary form. It Will of course be appreciated that theillustrated three by five array of and circuits is shown as only atypical arrangement, and any desired number of such circuits may beemployed, for multiplying numbers having any number of digits.

Signals representing the three digits of the multiplicand, in binaryform, are applied to input conductors a, 10b and 10c respectively. It isassumed that each of these digits will be either a zero (no potentialapplied to the input conductor) or a l (in which case'an electricalsignal is normally applied to the input conductor). Similarly, signalsrepresenting the five binary digits of the multiplier are applied to thefive control conductors 17a, 17b, 17c, etc. If the signal applied toline 17 is such as to actuate flip-flop circuit 19a to a conditionproducing an output in line 20a, then the application of that signal inline 20a will act through disabling circuits 28b, 28c, 28d and 28e toprevent the transmission of signals to lines 25b, 25c, 25d and 25e.Consequently, when .clock 24 is placed in operation and produces a firstpulse, the addition of that pulse to the signal in line 20a acts throughand circuit 23a to produce an output in line 25a. If flip-flop circuit12a is in an actuated condition producing a signal in line a, thatsignal will add to the signal from line 25a and produce an outputactuating or circuit 60 and adder 48 to register a one on theaccumulator 57. If no signal is present on line 15a, then the adder 48is not energized. Similarly, adders 41 and 33 are actuated by andcircuits 16f and 16k, in accordance with the signal provided byassociated line 15b or 15c.

As soon as the circuit 23a energizes line 25a, the signal on line 25a iscommunicated back through line 26a to delay element 27a. After apredetermined short delay period, unit 27a actuates bi-stable circuit19a to its original condition in which no output is provided on line a.The delay introduced in this manner is just sufl'lcient to prevent theenergization of the next successive line 20b until after the firstclock-pulse has been terminated, to thereby prevent the actuation of tworows of and circuits 16a, etc. simultaneously.

While a signal is present on line 20a, all of the other lines b, 25c,25d and 25e are maintained free of any signal which could actuate theirassociated and circuits 16b, etc., by virtue of the inhibitingcharacteristic of the signals supplied from line 20a to disablingcircuits 28b, 28c, 28d and 28e. As soon as the bi-stable circuit 192 hasbeen returned to a condition in which it no longer supplies aninhibiting signal to line 20a, disabling circuit 28b becomesineffectiveto prevent the transmission of a signal'to line 25b, andconsequently if bistable circuit 19b is in a condition to produce anoutput in line 20b, that output is transmitted to line 25b and to theassociated and circuits 16b, 16g and 161. At the same time, this signalwill inhibit all of the other successive lines 20c, 20d and 20c fromtransmitting their signals to lines 250,

25d and 25e. The signal on line 25b at the time of the next clock-pulse)will combine with whatever signals are present on lines 15a, 15b or 15cto actuate or not actuate and circuits 16b, 16g and 161, in accordancewith the signals applied to lines 15a, 15b and 16c. As in the case ofthe first control conductor, a delay re-set signal is applied throughline 26b to bi-stable circuit 19b, to automatically remove the signalfrom line 20b after a predetermined interval sufficient to avoidsimultaneous actuation of two control lines, to then allow the nextsuccessive control line to energize its associated and circuits. Thissuccessive actuation of the difierent horizontal rows of and circuitscontinues until the bottom row 16e, 16j and 16p is energized, at whichtime the signal from the final line 20c is removed, and this conditionis indicated by unit 31 which shows that the multiplication process hasbeen completed. If any one or more of the control lines 126a, 126b, etc.are in a zero condition (do not have one signals applied thereto) thenthe inhibiting circuitry acts to automatically skip over any such lines,and in each case skip down to the next successive control line whichdoes carry a one signal, without attempting to perform useless addingoperations at the zero lines. This avoids wasted intervals of time, andthus greatly speeds up the overall multiplication process.

By virtue of the pattern in which the ditferent and circuits 16a, etc.are connected to the adders or readout circuits 33, etc., eachsuccessive horizontal row of the and circuits acts to automaticallyshift the etfect of the different input conductors'15a, 15b and 15c tothe left one step. That is, whereas the three circuits 16a, 16f and 16kof the top row are associated with the three right adders 48, 41 and 33respectively, the an circuits 16b, 16g and 161 of the next row areassociated respectively with adders'49, 48 and 41. Similarly, eachsucceeding row of the an circuits is associated with adders which areshifted another step to the left. As all of the partial multiplicationsare efiected by energization of the lines 17a, 17b, 17c in sequence, thevarious partial products are applied to the adders in progressivelyshifted positions, and are added together by the adders to produce onthe product register the ultimate product of the overall multiplicationprocess. After this process has been completed, all of the variousbi-stable circuits are re-set by energization of the different re-setcircuits 14, 22 and 56.

In FIG. 1, the elements disclosed are logical elements in their mostgeneral sense, and the and circuits 16a, 16b, 16c, etc. are intended torepresent any logical elements operable to produce outputs correspondingto binary one digits in response to the presence of a signal on acorresponding input line 15a, 15b, 15c representing a binary one, and asignal on the corresponding control line 20a, 20b, 20c, etc.representing a binary one, if permitted by the balance of the controlcircuitry.

FIG. 2 represents fragmentarily a second form of the invention, in whichthe functions of the and circuits 16a, 16b, etc., and the or circuits59, 60, 61, 62, and 63 are performed by a matrix of magnetic cores 64.These cores may take the form of small rings of magnetizable material,preferably selected to have a hysteresis loop of the high loss typeillustrated in FIG. 3. This loop is desirably of the illustratedessentially rectangular configuration, having a sharp bend or knee atpoints 65 and 66, and having substantially horizontal bottom and topsides 67 and 68 and two substantially vertical sides 69 and 70.

The numbers 123a, 123b, 1230, 123d and 123e in FIG. 2 represent andcircuits corresponding to those shown at 23a, 23b, 23c 23d and 23e inFIG. 1. The inputs to these and circuits are the same as shown in FIG.1, and all of the rest of the apparatus illustrated to the left ofcircuits 23a, etc. in FIG. 1 is to be considered as present in FIG. 2,but for simplicity of illustration has been deleted from the drawing.Similarly, the delayed re-set lines 126a, 126b, 126e, 126d and 126e allcorrei at 9021, 9th), 90c, 9 3d and 90e.

- spond to lines 26a, 26b, etc. of FIG. 1, and function in the samemanner.

The output from and circuits 123a, 123b, etc. in FIG. 2 controls aseriesof electric switches represented One side of each of theseswitches is connected to a common line 71, while the second sides of theswitches are connected to five individual conductors 125a, 125b, 125e,125d and 125e passing through the various cores 64 in the arrangementshown. Into line 71 there are connected in series an oscillator 72 forproducing a sinusoidal alternating current output, and a direct currentbiasing power source represented at 73 as a battery. One side of thebattery is grounded at 74, as are the right ends of conductors 125a,125b,'etc. at 75. Thus, switch 90a is connected into a series circuitwith the oscillator 72 and battery 73, and acts to close the circuittrom the two power sources 72 and 73 to line 125a, and produce a flow ofcurrent therethrough, Whenever and circuit 123a is energized in themanner discussed in connection with circuit 23a of FIG. 1. Similarcircuits are formed including each of the other switches 90b, 990, etc.,and the power sources, together with the associated conductors 125b,125e, 125d and 125e. Each of the horizontal conductors 125a, etc. passesthrough one of the horizontal rows of cores 64, while each of the inputconductors 115a, 1115b and 115e passes through one of the verticalcolumns of cores. The three input conductors 115a, 115b and 115c areconnected to three bi-stahle circuits 112a, 112b and 112e, correspondingto circuits 12a, 12b and 12c of FIG. 1, and actuated in the samemanner.Line 115a is shown as extending downwardly through the cores, and thenreturning to bi-stable energizing circuit 112a to :form a completecircuit for passing current through the associated vertical row ofcoreswhenever bi-stable circuit 112a is in its actuated condition.Similar complete circuits are provided in conjunction with each of thelines 115b and 11c, but have been shown only partially in the drawing toavoid undue complication. The various adders 76 of FIG. 2 may beidentical with the adders 33, etc. of FIG. 1, and may have outputcircuits, bi-stable circuits, sum lines, carry lines, partial productlines, etc. associated therewith in the same pattern shown in PEG. 1.

The adders are actuated by read-out conductors 77 which extend throughthe cores in a diagonal pattern corresponding essentially to the patternof the readout lines 32, etc.

in. FIG. 1, to produce the same automatic shifting effect. Each or theread-out lines 7'7 may have a diode or other rectifier 78 connected intothe circuit, to provide pulses in only one direction to the adders, andeach read-out line may have associated therewith a return line as shownat 79 in connection with two of the adders, for completing the read-outcircuit.

Each of the cores 64-is so designed that a combination of two pulses orsignals in the two associated input and control conductors (for example115a and 125a, or 115b and 125a, etc.) will be suflicientto actuate thecore in question from a predetermined normal magnetic state to a secondand opposite magnetic state. However, one of these pulses alone can noteffect such an actuation. When the core is thus actuated, the change inmagnetic state functions to produce in the associated read-out line 77an output signal which is transmitted to one of the adders to berecorded thereby." 7

Each of the cores 64 is normally maintained magnetized in apredetermined direction, typically the direction of the magnetic staterepresented by the lower line 67 in the FIG. 3 hysteresis loop. To.simplifythe discussion, this magnetic state represented at 67 may betermed a neg- ,tive-.magneticstate, or negatively driven state, whilethe condition represented by upper line 68 may be called a positivestate. As will be understood, in order to actuate any one of the coresfrom negative state 67 to positive state 68, the magnetizing force H ormagnetizing current must be sufiiciently great to drive the core pastbend of the hysteresis loop, far enough so that the core changes to thepositive state represented at 68. The pulses fed to input lines 115a,115th and l15c are insufiicient by themselves to cause the cores to sopass bend 65, but will do so in combination with pulses (from thehorizontal control lines. The input signals supplied to lines 115a, 115band 1150 are converted to pulses by connection of switches 80 into theseconductors, with these switches being controlled by clock-pulsegenerator 124. The current signals which pass through lines 115a, 115 hand 1150 are uni-directional or direct current pulses.

A.C. oscillator 72 is connected to clock-pulse generator 124, tosynchronize the alternating current produced by oscillator 72 withrespect to the pulses from unit 124, and the signals in lines 115a, 115b and 1215c.

In FIG. 3, I have represented at 82 the D.C. biased alternating currentsinusoidal wave which is fed to control conductors 125a, 125b, 125c,etc. by oscillator 72 and battery 73, and I have represented at 83 theD.C. pulses which are fed to the vertical lines 115a, 115b, and 115c.The signal 82 has a D.C. component 84 supplied by attery 73, whichcomponent shifts the center of the A.C. cycle leftward to the point 85in FIG. 3. The A.C. component is preferably greater than the D.C.component. The combined A.C. and D.C. components of signal 26 provide amagnetizing force H which fluctuates between a left limit 86 and a rightlimit 87. When signal 82 reaches its left limit 86, the magnetizingforce H is sufiiciently great in a negative direction to causeassociated core 64 to magnetically pass upper bend 66 of the hysteresisloop, and thus actuate the core to its negative driven state representedat 67. This is true even though there may be no pulse 83 supplied by theassociated vertical wire a, 115b or 115c. However, the other extremityof pulse 82 in FIG. 3, that is, the right extremity represented at 84,does not provide a sufiicient magnetizing force H to *pass bend 65 ofthe hysteresis loop. and thus actuate the core to its positive state 68.Consequently, unless a pulse 83 is supplied to the correspondingvertical wire 115a, 115=b or 1150, the core is not actuated to itspositive state, even though a signal 82 is present. The pulses 82 thusserve to maintain each core 64 in its negative state 67, until a pulse83 is supplied simultaneously on the associated vertical wire 115a, l15bor 115e, atwhich time the combination of signals actuates the core toits positive state 68, following which the si nal 82 acts to return thecore to its negative driven state 67 (the pulse in line 115a, 115i) or11.5c being terminated by the clock pulse generator prior to thetermination of the biased alternating current signal 82).

The functioning of the FIG. 2 arrangement will be apparent. To perform amultiplication operation, first of all the multiplicand digits areapplied to bisstasble circuits 112a, 11% and 1122c, and the multiplierdigits are applied to control signal sources corresponding to thoseshown at 13a, 18b, 18c, 18d and 18ein FIG. 1. The automatic sequentialcontrol circuit or scanning circuit having the various disablingcircuits 281), etc, as shown in FIG. 1, causes the an circuits 123a,123b, 123e, etc. of FIG. 2 to be sequentially energized, upon successiveactuations of clockpulse generator 124, and in a manner skipping anycontrol circuits 'on which a zero signal is present. The first pulsefrom the clock-pulse generator 124 energizes and circuit 12 3a (if acontrol signal has been applied thereto), and thereby commences a cycleof the D.C. biased alternating current represented at 82 in FIG.

2. Simultaneously, the same clock-pulse .actuates switches 80 to supplyD.C. pulses-to such of the vertical lines 115a, llfb and 115c as havehad their bi-stable circuits 112a, 112 h and l12c actuated by inputsignals supplied thereto. Clock pulse generator 124 so synchronizes theD.C. pulses 83 with oscillator 73 as to assure that each pulse 83 addsto or-supplements the correspondingly directed portion of the D.C.biased A.C. signal 82. That is, pulse 83 ccr 9 ciirs'while the currentof signal 82 is in a direction such that the magnetizing effect of thesignal 82 is in thesame direction as that of pulse 83. Thus, these twocombined pulses cause the core to shift to its positive state 68,following which the pulse 83 terminates as signal 82 reverses to anegative state, so that signal 82 then returns the core to its negativestate 67 until the 'next pulse 83 occurs in that particular core. Suchactuation of a core 64 to its positive state 68 creates a magnetic fieldin the vicinity of that core which induces an electrical current in thecorresponding read-out line 77, to thus energize an associated one ofthe adders or read-out circuits 76. The diagonal arrangement of theread-out lines as they pass through the core matrix functions as in FIG.1 to cause a successive shifting of the results of the different partialmultiplication steps, so that the ultimate product is recorded by theregisters or accumulators associated with adders 76.

V For the, purpose of clarifying the meaning of the physical state of anobject, as used in the claims appended hereto, it is to be noted thatphysical state in its broad sense refers to the composition andconfiguration of the object, andthe values 'of the physical parametersto which it may be subjected, such as electric field, electricpotential, magnetic field, temperature, etc.

I claim:

1. Computer apparatus comprising an ordered series of input conductors,means for supplying electrical input signals to a plurality of saidinput conductors simultaneously and in any of several ditierentcombinations of the difierent input conductors, an ordered series ofseparately energizable control conductors, an array of logical andcircuits each responsive to one of said input conductors and one of saidcontrol conductors and each operable to produce a predetermined outputsignal in response to a predetermined combination of input and controlsignals from the associated input conductor and control conductor butnot in response to only one of said signals, a plurality of read-outcircuits actuable by different sets of said and circuits, each of saidread-out circuits being actuable by any one of the and circuits in anassociated set thereof which may be defined as including a first andcircuit actuable by one of said input conductors and one of said controlconductors, and as including all and only such other and circuits as areactuable respectively by pairs of conductors including an inputconductor which is a predetermined number beyond said one inputconductor in said first mentioned series and a control conductor whichis the same number beyond said one control conductor in said secondmentioned series; and scanning circuitry for controlling thetransmission of signals from said control conductors to.

the and circuits and operable to pass said signals from the controlconductors in a predetermined sequence of the control conductors, saidscanning circuitry including disabling means operable to prevent thetransmission of a signal from each of said control conductors to theand" circuits responsive thereto as long as any preceding controlconductor in said sequence is connected to the fand circuits fortransmission of a signal thereto, said disabling means beingautomatically operableto pass a signal from a particular controlconductor when the preceding control conductors are no longer connectedto the and circuits,

and said scanning circuitry including means for ceasing the transmissionof a signal from each control conductor to the and circuits after theand circuits have been actuated thereby. I V

2. Computer apparatus as recited in claim 1, in which said read-outcircuits are a plurality of adders each actuable by any one of the ancircuits in an associated one of said sets.

3. Computer apparatus as recited in claim 1, in which said read-outcircuits are a plurality of adders each actuableby any one of the andcircuits in an associated 'one of said sets, and a plurality ofindividual registers actuable'by said adders respectively.

ashed 4. Computer apparatus as recited in claim 1, in which saidread-out circuits are a plurality of adders each actuable by any one ofthe and circuits in an associated one of said sets, and a plurality ofindividual registers actuable by said adders respectively, each ofsaidadders having a sum line connected to and adapted to actuate theassociated register, and'having a carry line extending to the nextsuccessive one of said adders.

5. Computer apparatus as recited in claim 1, in which said scanningcircuitry includes a clock pulse generator for timing the intervals atwhich signals are transmitted from the control conductors to the andcircuits.

6. Computer apparatus as recited in claim 1, in which said scanningcircuitry includes a plurality of additional and circuits interposedbetween said control conductors respectively and the first mentioned andcircuits, and a clock pulse generator supplying intermittent timingsignals to said additional an circuits to control the intervals at whichsignals from the control conductors are transmitted to the"and circuits.7

7. Computer apparatus as recited in claim 1, in which said disablingmeans include a pluralityof and not circuits interposed between saidcontrol conductors respectively and said and circuits and each having adisabling connection to the preceding control conductors in saidsequence acting to disable a particular control conductor againsttransmission of a control signal to the and" circuits as long as asignal is received from oneof the preceding control conductors.

8. Computer apparatus as recited in-claim 1, in which said and circuitsare a matrix of magnetic cores having conductors in flux linkagerelation therewith carrying said input and control signals, each of saidcores being actuable between two different magnetic states by acombination of one input signal and one control signal but not by lessthan said combination.

9. Computer apparatus as recited in claim 8, in which said read-outcircuits are a plurality of adders each actuable by any one of the andcircuits in an associated one of said sets, and a plurality ofindividual registers actuable by said adders respectively. p

10. An electronic gang switch comprising an ordered series of inputconductors adapted to be separately energized, electrical signalsupplying means for energizing said input conductors and adapted tosupply input signals to a plurality of the input conductorssimultaneously in any of several dilferent possible combinations of thedifferent input conductors, an ordered series of control conductorsadapted to be separately energized, a matrix of individual elements eachresponsive toone of said input conductors and to one of said controlconductors, each of the individual elements being adapted to be actuatedfrom one physical state to a second physical state by a combination ofsimultaneous signals in those input and control conductors to which itresponds, but not being so actuable by less than said combination ofsignals, and a plurality of individual read-out units actuable by thechange in physical state of the elements, each of said read-out unitsbeing associatedwith a set of said elements which may be defined asincluding a first element associated with one of said control conductorsand one of said input conductors, 'and as including all and only suchother elements as are actuated by pairs of conductors including an inputconductor which is a predetermined number beyond said oneinput conductorin said first mentioned series and a control conductor which is the samenumber beyond said one control conductor in.

cally'responsive elements each responsive to one of said inputconductors and to one of said control conductors, each of the individualelements being. adapted to be actuated from one physical state to asecond physical state .by a combination of simultaneous signals in thoseinput and control conductors to which it responds, but not being soactuable by less than said combination of signals, electrical signalsupplying means for energizing said input conductors and adapted tosupply input signals to a plurality of the input conductorssimultaneously-in any of several different possible combinations of thediiferent input conductors, means operable to selectively energize anyof said different control conductors, a plurality of individual read-outconductors energizable by said change in physical state of the elements,a plurality of dilferent read-out circuits actuable separately by saiddifferent read-out conductors respectively, said read-out conductorsbeing arranged so that a predetermined plurality of the differentread-out circuits will be simultaneously actuated when a particularcontrol conductor and a articular group of input conductors areenergized, each of said read-out conductors .being associated with a setof said elements which may be defined as including a first elementassociated with one of saidcontrol conductors and one of said inputconductors, and as including all and only such otherelements as areactuated by pairs of conductors including an input conductor which is apredetermined number beyond said one input conductors in said firstmentioned series and a control conductor which is the same number beyondsaid one control conductor in said second mentioned series.

12. An electronic gang switch comprising an ordered series of inputconductors adapted to be separately energized, an ordered series ofcontrol conductors adapted to be separately energized, a matrix ofindividual cores each positioned in flux linkage relation to one of saidinput conductors and one of said control conductors, each of theindividual cores being adapted to be actuated from one magnetic state toa second magnetic state by a combination of simultaneous signals in theinput and control conductors which are in flux linkage relationtherewith, but not being so actuable by less than said combination ofsignals, electrical signal supplying means for energizing said inputconductors and adapted to supply input signals to a plurality of theinput conductors simultaneously in any of several diiferent possiblecombinations of the diflferent input conductors, a

plurality of individual read-out conductors passing in flux linkagerelation to different ones ofsaid cores, and a plurality of diiferentread-out circuits actuable separately .by said different read-outconductors respectively, said read-out conductors being arranged so thata predetermined plurality of the different read-out circuits will besimultaneously actuated when a particular control conductor and aparticular group of input conductors are energized, each of saidread-out lines being associated with a set of said cores which maybedefined as including a first core in fiux linkage relation with one ofsaid input conductors and one of said control conductors, and asincluding all and only such other cores as are in flux linkage relationrespectively with pairs of conductors including an input conductor whichis a predetermined number beyond said one input conductor in said firstmentioned series and a control conductor which in the same numberbeyondsaid one control conductor in said second mentioned series.

13. An electronic gang switch as recited in claim 12, in which saidcores are formed of magnetizeable material having high losssubstantially rectangular hysteresis loops. a

14. An electronic gang switch as recited in claim 12, in which saidcoresare formed of magnetizeable material having high loss'substantiallyrectangular'hysteresis loops and arranged essentially in rows extendingin predetermined X and Y directions, said input and control conductorsextending in said :X and Y directions respectively and along said rows.

15. An electronic gang switch as recited in claim 12,

including a composite'control signal source supplying electrical signalsto said control conductors selectively and including a first sourcesupplying an AC. wave and a second source superimposing a DC. componenton said A.C. wave to form a composite control signal which by itselfactuates said cores to said one state, said input signal sourcessupplying D.C. pulses to the input conductors in a direction tending tomagnetize the cores oppositely from said D.C. components of the controlsignal and of an intensity serving with said composite control signalsto energize the cores to said second magnetic state, and synchronizingmeans for timing said D.C. input pulses to occur simultaneously with theportion of the AC; cycle of said control signal which is in the samedirection as said input pulses.

16. Computer apparatus comprising an ordered series of input conductors,means for supplying electrical input signals to a plurality of saidinput conductors simultaneously and in any of severaldifierentcombinations of the different input conductors, an orderedseries of sep arately energizable control conductors, an array of logi'cal and elements each responsive to one of said input conductors and oneof said control conductors and each operable to produce a predeterminedoutputsignal in response to a predetermined combination of input andcontrol signals from the associated input conductor and controlconductor but not in response to only one of said signals, a pluralityof readout units actuable by, ditferent sets of said and elements, eachof said read-out units being actuable by any one of the and elements inan associated set thereof which maybe defined as including a first andelement actuable by one of said input conductors and one of said controlconductors, and as including all and only such other and elements as areactuable respectively by pairs of conductors including an inputconductorwhich is a predetermined number beyond said one input conductor in saidfirst mentioned series and a control conductor which is the same numberbeyond said one control conductor in said second mentioned series, andscanning means for controlling the transmission of signals from saidcontrol conductors to the and" elements and operable to pass saidsignals from the control conductors in a predetermined sequence of thecontrol conductors, said scanning means including disabling meansoperable to prevent the transmission of a signal from each of saidcontrol conductors to the and elements responsive thereto as long as anypreceding control conductor in said sequence is connected to the andelements for transmission of a signal thereto,' said disabling meansbeing automatically operable to pass a signal from a particular controlconductor when the preceding control. conductors are nolonger connectedto the ,and elements, and'said scanning means including means forceasing the transmission of a signal from each control conductor to theand elements after the and elements have been actuated thereby.

17. A logical information handling system comprising a plurality ofinput lines, a plurality of control lines, a matrix of logical elementseach normally in a predetermined condition und operable from saidpredetermined condition to a second condition and then back to saidpredetermined condition in response to complementary signals oncorresponding sets of said input lincsaand said control lines, means forsupplying said complementary signals to said input lines and saidcontrol lines and operable only through a complete two-way cycle toalways return said 13 of the readout lines, and separate readout unitsresponding to said readout lines respectively to produce difierentultimate responses of the overall informationhandling system toactuation of said lines.

18. An electronic gang switch comprising a series of input conductorsadapted to be separately energized, electrical signal supplying meansfor energizing said input canductors and adapted to supply input signalsto a plurality of the input conductors simultaneously in any of severaldifierent possible combinations of the difierent input conductors, aseries of control conductors adapted to be separately energized, amatrix of individual elements each responsive to one of said inputconductors and to one of said control conductors, each of the individualelements being adapted to be actuated from one physical state to asecond physical state and back to said first state by a combination ofsimultaneous signals in those input and control conductors to which itresponds, but not being so actuable by less than said combination ofsignals, and a plurality of different readout lines actuable by thechange in physical state of the elements in difierent groupsrespectively of said elements, whereby actuation of any of a pluralityof said elements in a particular one 0 said groups between said physicalstates will actuate a corresponding one of said readout lines but notanother of the readout lines, and separate readout units responding tosaid readout lines respectively to produce difierent ultimate responsesof the overall gang switch to actuation of said readout lines.

19. In a computing device wherein information expressed by a series ofcoded bits arranged in columnar array is transmitted from place toplace, a column shift device consisting of a matrix of magnetic binarieshaving columnar inputs each threaded through a difierent row of saidbinaries in one coordinate direction and each given a difierent digitalvalue, a plurality of column shift control inputs each threaded througha different row of said binaries in another coordinate direction andeach given a difierent digital value, and a plurality of columnaroutputs each shifted in space from the said columnar inputs and eachthreaded through a plurality of said binaries each of which isidentified by a digital value having a predetermined relation to thedigital values of its columnar input and its column shift control input,and means for successively transferring a plurality of bits in columnararray to a difierent columnar array consisting of means for successivelyenabling said columnar inputs and coincidentally pulsing a given one 0said control inputs.

20. A logical information handling system comprising a plurality ofinput lines, a plurality of control lines, a matrix of logical elementseach normally in a predetermined condition and operable from saidpredetermined condition to a second condition in response tocomplementary signals on corresponding sets of said input lines and saidcontrol lines, means for supplying return signals to one of said sets oflines of a value to actuate said logical elements from said secondcondition back to said predetermined condition without assistance fromcomplementary signals on the other set of lines, a plurality ofdifierent readout lines actuable by diflerent groups respectively ofsaid logical elements during at least a portion of their period ofactuation from said predetermined condition to said second condition andback to said predetermined condition, whereby actuation of any one of aplurality of said elements in a particular one of said groups willactuate a corresponding one of said readout lines but not another of thereadout lines, and separate readout units responding to said readoutlines respectively to produce difierent ultimate responses of theoverall information handling system to actuation of said lines.

References Cited by the Examiner T he following seferences, cited by theExaminer, are of record in the patented file of this patent or theoriginal patent.

UNITED STATES PATENTS 2,691,156 10/54 Saltz et a1 340-474 MALCOLM A.MORRISON, Primary Examiner.

WALTER W. BURNS, JR, Examiner,

